SN74LS74AN / 76AN Dual JK Flip Flop with Preset and Clear SN74LS76N 74LS76 7476 Counter Shift Register Frequency Divider

The SN74LS76AN containe two independent negatice edge triggered flip flops. The J and K inputs must be stable one setup time prior to the high-to-low clock transition. The preset and clear are asynchronous active low inputs. When low they override the clock and data inputs forcing the outputs to the steady state levels shown in function table.

Specifications

- Package: DIP 16
- High level input voltage: min 2V
- Low level input voltage: max 0.8V
- High level output current: -0.4mA
- Low level output current: max 8mA
- Clock frequency: max 30MHz
- Operating Voltage: 4.75V to 5.25 V
- Operating temperature: 0 to 70 degree celcius